The invention relates generally to semiconductor device fabrication and, in particular, to methods for fabricating a back-end-of-line (BEOL) interconnect structure that includes an on-chip passive element, BEOL interconnect structures that include a passive element and design structures for a radiofrequency integrated circuit (RFIC).
On-chip passive elements, such as thin film resistors and metal-insulator-metal (MIM) capacitors, are deployed in many types of integrated circuits, such RFICs. MIM capacitors and thin film resistors are integrated into one of the dielectric layers in a metallization level of the BEOL interconnect structure using the BEOL metallurgy. BEOL interconnect structures are routinely fabricated by damascene processes. For example, dual damascene process etch vias and trenches in a dielectric layer using reactive ion etching (RIE), which are concurrently filled with a conductor using a single blanket deposition and planarized. This process step is replicated to stack different metallization and via levels to create a multi-level, high density framework of metal interconnections.
During the fabrication of a metallization level, a thin film resistor is formed by depositing and patterning a conductive material with a relatively high resistance to a desired size and geometrical shape. Similarly, a MIM capacitor may be formed that includes a stacked structure consisting of plates of a conductor, which operate as electrodes, and an interplate dielectric layer situated between the plates.
Improved methods are needed for fabricating BEOL interconnect structures that include on-chip passive elements, as well as improved BEOL interconnect structures that integrate passive elements and RFIC design structures.